Technical Field
This invention relates generally to the field of semiconductors, and more particularly, to approaches used in forming a self-aligned via (SAV) and air gap within a semiconductor device.
Related Art
As process dimensions continue to shrink, litho-etch patterning for semiconductor devices is typically required to print 64 nanometer (nm) pitch metal layers (Mx levels) or below. However, poor overlay can be a significant factor for consideration in successful patterning applications. For example, without self-aligned via (SAV) processes, the dielectric space between copper lines and vias may become small, which can cause reliability issues. Furthermore, current SAV processes are typically self-aligned only in one direction. A weak point for the reliability failure mechanism of time dependent dielectric breakdown (herein “TDDB”) can form due to the proximity of the via bottom to an unrelated metal beneath it. A breakdown can occur along this interface leading to increased leakage or a dead short, thus compromising product functionality.